The present invention relates to a semiconductor design technology, and more particularly, to a frequency multiplier and multi phase clock generator for use in a semiconductor device that uses Delay Locked Loop (DLL).
Generally, a semiconductor device such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) receives an external clock and uses it as a reference clock to match various operation timings.
However, when a plurality of circuits provided in the semiconductor device is operated by using such an external clock, clock skew may occur due to its delay in a path through which the external clock is transmitted. In order to compensate for this clock skew, the semiconductor device is provided with a clock synchronizing circuit.
Such a clock synchronizing circuit can be implemented in two ways such as Phase Locked Loop (PLL) and DLL. Therefore, the semiconductor device performs various signal transmission/reception operations with external devices by using an internal clock synchronized with an external clock provided by the clock synchronizing circuit.
Basically, the PLL and DLL are similar to each other in configuration and operation, but distinguishable from each other in that the PLL uses a Voltage Controlled Oscillator (VCO) in generating an internal clock corresponding to an external clock, while the DLL utilizes a Voltage Controlled Delay Line (VCDL).
FIG. 1 is a block diagram showing a frequency multiplier and multi phase clock generator for use in a semiconductor device which employs DLL according to the prior art.
Referring to FIG. 1, the prior art frequency multiplier and multi phase clock generator includes a clock delay unit 100, having a plurality of delay units UNIT_DLY<1:N> connected in series, where each delay unit has a delay amount that varies depending on a level of a control voltage CTRL_VOL, for delaying a source clock REF_CLK to output a feedback clock FEDB_CLK and mixing multi phase clocks MTPS_CLK<1:N−1> from the respective delay units UNIT_DLY<1:N> to output a frequency multiplication clock FREQ_MTP_CLK; a phase detector 120 for detecting a phase difference between the source clock REF_CLK and the feedback clock FEDB_CLK to generate phase detection signals LVUP and LVDN; and a voltage level adjustor 140 for adjusting a level of the control voltage CTRL_VOL in response to the phase detection signals LVUP and LVDN.
Here, the phase detection signals LVUP and LVDN outputted from the phase detector 120 are provided as an up phase detection signal LVUP and a down phase detection signal LVDN based on a phase difference between the source clock REF_CLK and the feedback clock FEDB_CLK, where active intervals of each of the phase detection signals clock LVUP and LVDN do not overlap those of the other one of the phase detection signals clock LVUP and LVDN.
To be more specific, the phase detector 120 compares a reference edge of the source clock REF_CLK with a reference edge of the feedback clock FEDB_CLK, wherein the reference edge is generally a rising edge. Alternatively, the reference edge in another example, may be a falling edge. If a reference edge of the feedback clock FEDB_CLK lags behind a reference edge of the source clock REF_CLK, the phase detector 120 activates the up phase detection signal LVUP, and if a reference edge of the feedback clock FEDB_CLK precedes a reference edge of the source clock REF_CLK, it activates the down phase detection signal LVDN.
At this time, the length of active intervals of the up phase detection signal LVUP and the down phase detection signal LVDN varies depending on a difference between reference edges of the source clock REF_CLK and the feedback clock FEDB_CLK. That is, if a difference between them is relatively large, the length of active intervals of the up phase detection signal LVUP or the down phase detection signal LVDN becomes relatively larger. On the other hand, if a difference between them is relatively small, the length of active intervals of the up phase detection signal LVUP or the down phase detection signal LVDN becomes also relatively smaller.
The voltage level adjustor 140 is provided with a charge pumping unit 142 and a loop filter 144. The charge pumping unit 142 generates a control current CTRL_I having a magnitude corresponding to the length of active intervals of the up phase detection signal LVUP and the down phase detection signal LVDN, and supplies it to the loop filter 144. Then, the loop filter 144 performs a charging or discharging operation depending on the magnitude of the control current CTRL_I to adjust a level of the control voltage CTRL_VOL.
The clock delay unit 100 is provided with a plurality of delay units UNIT_DLY<1:N> 102 connected in series, and a frequency multiplication clock generator 104 for mixing multi phase clocks MTPS_CLK<1:N−1> outputted from the respective delay units UNIT_DLY<1:N> 102 to generate a frequency multiplication clock FREQ_MTP_CLK.
At this time, as the level of the control voltage CTRL_VOL rises, each of the delay units UNIT_DLY<1:N> 102 provided in the clock delay unit 100 has a decreased delay amount; and as the level of the control voltage CTRL_VOL decreases, each of the delay units UNIT_DLY<1:N> 102 has an increased delay amount.
Therefore, as the level of the control voltage CTRL_VOL rises, the entire delay amount of the clock delay unit 100 decreases and thus a delay time of the source clock REF_CLK decreases to generate the feedback clock FEDB_CLK. Similarly, as the level of the control voltage CTRL_VOL decreases, the entire delay amount of the clock delay unit 100 increases and thus a delay time of the source clock REF_CLK increases in generating the feedback clock FEDB_CLK.
Also, as the level of the control voltage CTRL_VOL rises, the phase difference between the multi phase clocks MTPS_CLK<1:N−1> outputted from the respective delay units UNIT_DLY<1:N> 102 provided in the clock delay unit 100 decreases. Likewise, as the level of the control voltage CTRL_VOL decreases, the phase difference between the multi phase clocks MTPS_CLK<1:N−1> from the respective delay units UNIT_DLY<1:N> 102 provided in the clock delay unit 100 increases.
Therefore, as the level of the control voltage CTRL_VOL rises, the frequency of the frequency multiplication clock FREQ_MTP_CLK rises. Similarly, as the level of the control voltage CTRL_VOL decreases, the frequency of the frequency multiplication clock FREQ_MTP_CLK decreases.
Now, the operation of the frequency multiplier and multi phase clock generator for the semiconductor device that uses DLL according to the prior art having the above-mentioned configuration will be described in detail.
FIGS. 2A to 2C are timing diagrams describing the operation of the frequency multiplier and multi phase clock generator for the semiconductor device that uses DLL according to the prior art shown in FIG. 1.
FIG. 2A shows a case where the prior art frequency multiplier and multi phase clock generator normally operates, and FIGS. 2A and 2B illustrate cases where it operates abnormally due to occurrence of harmonic locking.
First, the basic operation of DLL will be explained. Such DLL is used for synchronizing a reference edge of the source clock REF_CLK with a reference edge of the feedback clock FEDB_CLK, and performs the operation of increasing or decreasing the delay amount of the clock delay unit 100 for achieving the above purpose.
At this time, the feedback clock FEDB_CLK is generated by delaying the source clock REF_CLK. Therefore, when comparing them, a reference edge of the feedback clock FEDB_CLK always lags behind a reference edge of the source clock REF_CLK. Due to presence of a minimum delay amount of the delay unit 100, a reference edge of the source clock REF_CLK cannot be synchronized with a reference edge of the feedback clock FEDB_CLK.
Thus, this DLL is operative to synchronize a reference edge of the source clock REF_CLK which lags behind its original reference edge by one clock cycle 1 tck with a reference edge of the feedback clock FEDB_CLK. Upon completion of the locking operation of the DLL, the phase difference between the source clock REF_CLK and the feedback clock FEDB_CLK should be exactly one clock cycle 1 tck. That is, the phase difference should have the state as shown in FIG. 2A.
At this time, in the state of FIG. 2A, since the delay amount of the clock delay unit 100 is kept atone clock cycle 1 tclk, if the number of delay units UNIT_DLY provided in the clock delay unit 100 is N, a delay amount of each of the delay units UNIT_DLY<1:N> becomes 1 tck/N and a phase difference between the multi phase clocks MTPS_CLK<1:N−1> also equals a time interval corresponding to 1 tck/N. Also, the frequency of the frequency multiplication clock FREQ_MTP_CLK outputted from the clock delay unit 100 becomes N/2 of the frequency of the source clock REF_CLK.
However, such DLL is not normally locked due to external effects such as variations in Process, Voltage, Temperature (PVT) or unknown malfunction causes, and may thus be harmonic locked, as in FIGS. 2B and 2C.
First, referring to FIG. 2B, it can be seen that the DLL should operate in a way that the reference edge of the feedback clock FEDB_CLK can be synchronized with the reference edge of the source clock REF_CLK which lags behind its original reference edge by one clock cycle 1 tck, but is operative to synchronize the reference edge of the feedback clock FEDB_CLK with the reference edge of the source clock REF_CLK which lags behind its original reference edge by one clock cycles 2 tck.
In this case, upon completion of locking operation of the DLL, the phase difference between the source clock REF_CLK and the feedback clock FEDB_CLK is two clock cycles 2 tck, which becomes twice one clock cycle 1 tck as intended.
Also, in the state of FIG. 2B, the delay amount of the clock delay unit 100 is kept at two clock cycles 2 tck of the source clock REF_CLK. Therefore, if the number of delay units UNIT_DLY provided in the clock delay unit 100 is N, the delay amount of each of the delay units UNIT_DLY<1:N> becomes 2 tck/N and the phase difference between the multi phase clocks MTPS_CLK<1:N−1> also equals a time interval corresponding to 2 tclk/N. In addition, the frequency of the frequency multiplication clock FREQ_MTP_CLK outputted from the clock delay unit 100 becomes N/4 of the frequency of the source clock REF_CLK.
That is, in the state of FIG. 2B, there is a problem that the phase difference between the multi phase clocks MTPS_CLK<1:N> becomes twice larger than that as originally intended, and the frequency of the frequency multiplication clock FREQ_MTP_CLK also becomes twice smaller than that as originally intended.
Next, referring to FIG. 2C, it can be seen that the DLL should operate in a way that the reference edge of the feedback clock FEDB_CLK can be synchronized with the reference edge of the source clock REF_CLK which lags behind its original reference edge by one clock cycle 1 tck, but is operative to synchronize the reference edge of the source clock REF_CLK with the reference edge of the feedback clock FEDB_CLK.
In this case, since the minimum delay amount of the clock delay unit 100 is not 0, there is a problem that the locking operation of the DLL cannot be completed. Thus, the normal multi phase clocks MTPS_CLK<1:N−1> and frequency multiplication clock FREQ_MTP_CLK cannot be generated.
As described above, in order to prevent occurrence of harmonic locking in DLL operation, the prior art frequency multiplier and multi phase clock generator employed the method which enables a locking operation to be normally performed by resetting the delay amount of the clock delay unit 100 to the initial state through the use of a separate reset signal upon detection of harmonic locking occurred.
This method of using the separate reset signal must not only additionally include a circuit which detects occurrence of harmonic locking but also initialize the DLL by applying such a reset signal thereto each time harmonic locking has occurred. However, this existing method cannot predict when harmonic locking has occurred and also has difficulty in controlling timing since harmonic locking may again occur due to external impacts even when locking operation is normally completed by the initialization process.